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"Substrate influence on the behavior of capacitance hysteresis of III-V bilayered MOS stacks"
Fernando L. Aguirre, Sebastián M. Pazos, Felix Palumbo, Igor Krylov and Moshe Eizenberg
Proc. of the "32nd Symposium on Microelectronics Technology and Devices" (SBMicro 2017), Fortaleza, Ceara, Brazil, August 28-September 1, 2017.
"Microelectronics Technology and Devices (SBMicro), 2017 32nd Symposium on", Published by the Institute of Electrical and Electronics Engineers (IEEE). (2017) 1-4
ISBN: 978-1-5386-2877-5 (on-line)
978-1-5386-2878-2 (pod)
Abstract
The dependence of ΔVHys on the stressing voltage for High-k Bi-layered InGaAs and InP substrate MOS capacitors is discussed in this work. Using different proportions of Al2O3 and HfO2 dielectrics on a 10 nm thick gate insulator, the influence of each layer and its defects on the variations of the flat-band and hysteresis voltage is studied. Results show that increasing the thickness of the Al2O3 interfacial layer improves the quality of the structure in terms of reducing the hysteresis. InP stacks show the same tendencies of InGaAs stacks, but with a negligible impact of the stress in inversion on the hysteresis.
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